As is known in the art, integrated circuits based on Silicon On Insulator (SOI) CMOS or standard silicon Complementary Metal Oxide Semiconductor (CMOS) processing typically addresses the issue of multiple supply voltages and multiple digital logic levels in various ways. SOI technologies are able to incorporate full-trench or partial trench isolation [see S. Maeda., et, al., “Feasibility of 0.18 um SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications,” IEEE Transactions on Electron Devices, vol. 48, no. 9 Sep. 2001, pp. 2065-2073] resulting in either floating-body field-effect transistors (PET) or body-tied FET devices, with a terminal provided for the body of the transistor (FIG. 1). Alternatively, standard CMOS devices, which have a common p-type bulk connecting the body terminal of all nMOS transistors, use an additional deep n-type well implant to create a triple well structure [see U.S. Pat. No. 5,281,842, Yasuda, et. al, “Dynamic Random Access Memory with Isolated Well Structure” and U.S. Pat. No. 6,218,895 B1, De, et, al, “Multiple Well Transistor Circuits Having Forward Body Bias”] This additional well allows for an isolated nMOS device, which combined with standard pMOS devices, enables multiple supply voltages and logic voltage levels on a single integrated circuit (FIG. 2).
Silicon dioxide trench isolation can also be used to improve the quality factor of passive devices or structures formed above the silicon substrate. The trench isolation is placed directly below the passive devices to reduce the losses associated with the low resistivity substrate or any surface charge that may exist below the passive device, thus improving the quality factor of the component.
Although the approaches outlined above work well for SOI CMOS and standard CMOS technologies, they are not attractive solutions for III-V/CMOS heterogeneous integration technology. Recent research efforts have demonstrated the efficacy of a GaN-CMOS heterogeneously integrated technology [See T. Kazior, et. al., “High performance mixed signal and RF circuits enabled by the direct monolithic heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate,” IEEE CSICS, 2011], which enables the incorporation of GaN HEMT devices on the same silicon substrate as CMOS devices. The GaN HEMT devices are created on a GaN epitaxial buffer layer, which is grown in a window region of a silicon-on-insulator (SOI) wafer. The CMOS components are fabricated using a standard CMOS process flow in the thin silicon layer above the buried oxide layer (BOX).
Unlike fully-depleted and thin-film SOI CMOS devices, in which the source and drain implants extend all the way to the buried oxide layer, the source and drain implants of the CMOS devices only extend partially through the top silicon layer (similar to a thick-film SOI technology). This creates a shallow p-type material shared between all of the silicon components, essentially acting as a shallow bulk substrate for the CMOS components.
Although it may be possible to add full-trench isolation or an additional n-well implant to the process flow, it is undesirable. The incorporation of a full-trench isolation or an additional well implant will require additional masks and fabrication steps (resulting in higher costs), as well as additional processing complexity. The thickness of the GaN buffer layer and the thickness of the top-level of silicon material will need to be balanced against the full-trench isolation depth or the deep n-well implant depth during processing, creating additional constraints to the technology. The ability to create isolated FET devices and high quality passive devices, such as capacitors and inductors, without the use of full-trench isolation or deep well implants, would be advantageous to a heterogeneously integrated GaN-CMOS technology.